Defacto’s SoC Compiler is a complete SoC integration platform multidimensional and pre-synthesis with a high level of automation taking in consideration all design information, including RTL, IP-XACT, timing constraints, power, physical, and test.
Before logic synthesis, SoC Compiler enables full implementation capabilities towards IP and connectivity insertion, design editing, views generation with real-time monitoring of the integration progress.
This enables SoC creation in minutes and maximizes design reuse from existing projects.
High Level Benefits
- Assist reaching best possible PPA combination within a tight schedule
- Bring more automation into SoC Integration flow before logic synthesis
- Augment existing front-end SoC assembly and integration flows towards a more unified integration process by considering several design collaterals RTL, IP-XACT, SDC, UPF, LEF/DEF, etc.
- Get up to 90% and higher of design reuse including RTL and design collaterals
- Easily migrate internal scripts and tools with the support of rich APIs high and low level: Python, Tcl, Perl, C++, Java, etc.
- Reduce drastically TAT and engineering effort by minimizing design iterations
- Enable non-experts to perform design engineering tasks (power, architecture, testing, etc.) through simple APIs
- Enables SoC creation even if design blocks and views are missing
High Level Key Features
- Multi-format IP cores insertion including Verilog, System Verilog, VHDL, IP-XACT 2009, IP-XACT 2014, even mixed and uncompleted.
- Automated and hierarchical connectivity insertion including System Verilog and IP-XACT interfaces
- Real-time monitoring of the SoC integration progress
- Physically, Power and Timing-aware integration process at RTL
- Design Reuse and Packaging of IP cores and subsystems.
SoC Compiler provides unique capabilities to build a complete SoC at RTL with all the mechanisms to edit the design and deliver a correct-by-construction RTL and the associated views such as SDC and UPF, ready for synthesis.
- Full language support
- Verilog, SystemVerilog, VHDL or a mix
- Any input is supported: IP-XACT, UPF, SDC, LEF/DEF, .lib
- No need to package IP before integration
- Top level creation from scratch or using existing top RTL
- IP Integration with full parameterization of instances
- Automatic connectivity insertion
- Automatic core and memory wrapping
- “on the fly” design refactoring
- Generation of different integration configurations based on Power, Physical, Timing information
- Generation of the Top level RTL view
- Generation of the design views as well: IP-XACT, UPF, SDC
SoC Compiler enables the SoC design assembly process with full support of IP-XACT standard in full compliance with RTL files. Several automated design “extraction, packaging and reuse” capabilities are provided. Defacto is part of the Accellera committee for the definition of IP-XACT standard and an active member of the IP-XACT 2021 version
- Full language support
- IP-XACT 2009 / 2014
- Vendors extension
- IP-XACT component and design creation from scratch
- IP-XACT can be read instead or in parallel with RTL
- Automatic connectivity insertion using standard busses, ad-hoc, etc.
- View translation between IP-XACT & RTL
- Coherency checks between RTL and IP-XACT
- Design attributes unification
- Generation of IP-XACT top level view
During the SoC integration process, SoC Compiler automates the management of power intent through an automated generation, update, promotion and demotion of UPF files. Power Intent Static Checks and UPF-vs-RTL coherency checks are also provided as part of the power integration process.
- Demote or extract UPF from Top level
- Promote UPF from block/IP to Top level
- Update UPF whenever a design is modified
- Generate UPF from scratch
- Complete Power intent checks including UPF linting and coherency checking with RTL and Liberty files.
SoC Compiler enables several clock management capabilities as part of the SoC integration process. Clock-tree exploration, checking and generation of timing constraints are provided, including demotion and promotion of SDC.
- Clock tree exploration
- Identification of clock sources and potential pin constraints
- Dedicated DRCs for master / generated clock path checks
- RTL vs. SDC Coherency Checks
- GUI based exploration and debug environment
- Update SDC files whenever a design is modified
- Generate SDC files from scratch
- Demote or extract SDC files from the top level
- Promote SDC files from different IPs to the top level
SoC Compiler enables the consideration of physical design information which are contained in LEF/DEF file to let the SoC integration process lead to better PPA results.
- Data extraction from LEF/DEF
- Data extraction from Design
- Automated LEF/DEF design restructuring
- Coherency checks between physical design information and gate-level or RTL design information.
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