Welcome to everybody!
STAR is a solution that addresses many languages as Verilog, System Verilog, Vhdl, mixed or gate level.
The STAR Perl APIs covers any design editing need at RTL(IP reuse, connectivity, grouping, wrapping, grouping, cleaning, ...). It replaces complex and hard to maintain in-house scripts and tools. Through basic and advanced editing capabilities, this tool shortens the path to synthesis-ready RTL code for complex IPs and SoCs.
The STAR Perl APIs allows also a full exploration of your design through intuitive Perl APIs. This can be used for example to build any custom report at RTL or even to capture any design information at a stage of the flow.
Finally the user can then save all the design into an internal database that he can restore later quickly.
The STAR Perl APIs allows also a full exploration of your design through intuitive Perl APIs. This can be used for example to build any custom report at RTL or even to capture any design information at a stage of the flow.
Finally the user can then save all the design into an internal database that he can restore later quickly.
Here are some typical examples of how to use the Perl APIs STAR interface:
