Part II - RTL Design Rule Checking & Reporting

1. Read RTL/Gate Level Design
2. Top level specification
3. Design Rule checking - Customize DRC severity

1) Read RTL/Gate level design

STAR-Tcl is able to read a design that can be verilog, system verilog, vhdl, or mixed. 
The tool can also read gate level design (user must read the verilog bahavior model of the cells). 

There are 2 ways of reading the files :

• Using file list : Use language switch to move from a language to another
  
  In your main tcl script, you should read your file list as follows: read_verilog -f "filelist_name"

• Using read_hdl command : It allows to read among all languages
  
  Many options are available for these commands. To get the list of all the available options for these command, use the command help: help command_name

2) Top Level Specification

At this stage, you managed to read your file. To setup the top level specification, the user should use the set_top_level command. 
The set_top_level command will call an elaboration engine that will create the real hierarchy of the design (propagate the parameters from the top to all design underneath)

• Read the design and set the top level

If I have undefined designs or if I want to black_box some designs like analog blocks or memories, how should I proceed? 

• Set top level black_boxing all undefined designs

• Set top level black_boxing specific modules

3) Design Rule Checking

There are 2 categories of DRCs that STAR performs. VERI and RTL. 
- VERI reports information about compilation and elaboration steps of the HDL. 
- RTL (deprecated) reports information about the RTL itself (Dangling port, multiples drivers, undriven, ...)

Important: For previous users of STAR Product, the RTL DRCs are no longer available through STAR Framework TCL.

• Example of Design Rule Checking for ac97

Note: 
The user can customize the DRCs using set_message_reporting