Part II - Input/Output File Handling

1. Read RTL
2. Top Level Specification
3. Write Update RTL

1) Read RTL

ADE is able to read a design that can be Verilog, System Verilog, Vhdl, or mixed. 

There are 2 ways of reading the files :

1. Using the file list

1. Explicitly reading each file

2) Top Level Specification

At this stage, you managed to read your file. To setup the top level, the user can either explicitly tell the tool what the top level is, or let the tool try to select the top level

• Let the tool pick a top level

• Provide the tool with a top level

3) Write updated RTL

If the user choses to make any RTL edits beyond just RTL exploration, then there are several mechanisms to choose how the new edited RTL should be generated and written out. Below is a snap shot of some of the most commonly used APIs.