STAR provides a large set of structural verification capabilities at RTL. The provided checks are fully automated. On top of that, the user can build and run custom checks at RTL.



Typical Cases

Connectivity checking

  • Verify and debug complex I/O Muxing configurations
  • Extract connectivity between instances, tied and opens over all levels of hierarchy
  • Trace and report issues for custom structures

Clock path extraction

  • Generate a report containing clock/reset drivers of all sequential elements
  • Trace and debug connectivity between defined master and generated clocks

Compare designs

  • Monitor the integration status between different design versions
  • Pinpoint the relevant differences between the modified IPs 



Key Features

  • Simulation-free connectivity checks with constraint propagation
  • High-level extraction commands (block interconnectivity, clock path, open/tied...)
  • Tracing capabilities (direct connections, final drivers/loads, fanin/fanout...)
  • Schematic Graphical Interface
  • Excel API to extract the connectivity requirements to check




  • Avoid the detection of connectivity issues too late in the design process
  • Move useless simulation tasks to simulation-free press button structural checks
  • Add confidence and robustness around critical structures
  • Extract relevant information like connectivity reports



More on Semiwiki: "Analysis and Signoff for Restructuring


For More Information :

Contact us or Access to Videos and Datasheets