Maintaining a continuous correlation between power intent (UPF and RTL) is a critical need for all ASIC design teams. Using STAR, the logic design hierarchy and power strategy are tightly linked to each other, so users can intuitively view and explore the mutual relationship. For example, any change of a UPF or an RTL code is automatically highlighted and reported by the tool.


Key Capabilities

  • Complete UPF support (up to 3.0)
  • Extensive UPF parsing checks
  • Unified power-intent and logic design databases standards
  • Intuitive power-intent schematics linked with std logic design schematics
  • Hierarchical or flat power-intent representation
  • Quick pin-pointing of power control signals and RTL design elements
  • Power and logic design schematic cross-checks 



  • Speed-up power-intent debug process 
  • Increase productivity by helping engineers visualize links between RTL and UPF 


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