To deliver greater functionality for next-generation applications such as automotive and mobile, leading-edge SoCs with higher performance at much lower power are needed. Meeting time-to-market requirements is critical to avoid wasting investments due to late delivery. To ensure competitiveness, lowering the overall cost is an essential factor for success. In such a context, SoC design groups continue facing high pressure to quickly innovate and consistently deliver. Breakthrough design methodologies and innovations are needed more than ever.
In current design flows, RTL design is where most of the innovation is expected since it provides flexibility with the highest reusability potential. More precisely, typical market expectations are during front-end and RTL design in particular:
- Standardize as much as possible design flows and design methodologies
- Increase design reuse ratio from one project to another
- For complex SoCs, shorten the gap between design assembly & design implementation
- Make design tasks technology-independent by moving to higher abstraction levels such as RTL
- Help facing challenges when handling sophisticated RTL coding styles
- Through a unified & persistent database, conciliate RTL with a variety of multi-domain design standards describing power intent, timing constraints, physical information, software registers…
Defacto’s latest Release STAR 8.0 helps to lower the complexity of typical SoC Integration design flows where several sources of design information are required to start building an SoC, including design descriptions (mixed RTL code, gate-level netlist, physical) and design collaterals (power intent, timing constraints).
Traditionally, design information such as port descriptions and attributes are duplicated and modified while being handled by different design teams. This process may lead to incoherent and inconsistent design decisions. STAR 8.0 provides a unified API that helps to build a consistent and unified data structure where several design views can be considered and generated. STAR 8.0 offers a full abstraction of design formats without losing design information. A typical example is the Accellera IPXACT standard, which is more and more part of the standard package for IP cores and IP subsystems.
STAR provides a fully automated IPXACT-RTL mutual view generation. Any information on an external or an internal IP is automatically transformed into RTL and vice-versa. Extending an existing RTL design flow becomes transparent and straightforward. The same transformation methodology is made possible with other views such as CSV/Excel or with design collaterals such as UPF or SDC. Based on a unified data structure with full support of RTL attributes for design objects, multisource design information is parsed and compiled, and RTL code is fully instrumented and documented. Any inconsistency between design views and design descriptions is flagged and reported in real-time.
Given such a unified infrastructure and API, any SoC design decision like multisource TOP level generation, IP insertion, or structural checks such as connectivity, becomes straightforward.
“As far as we know, Defacto’s STAR is a unique SoC integration platform in the market which conciliate between RTL and different standards and design collaterals starting from the SoC assembly process to a full RTL implementation including the generation of ready for synthesis RTL code” as stated by Chouki Aktouf, President & CEO of Defacto. “We are proud to announce STAR 8.0, which provides a complete set of design features that are key today in the SoC Build & Signoff process. Beyond new unique features, a much higher degree of customization can now be reached by designers with a complete set of supported APIs such as Python, Perl, Java and C++”.
Defacto will be demonstrating its STAR 8.0 Design Solutions in several upcoming events this year, such as DATE (Design & Test in Europe) by March 10, 2020, in Grenoble and DAC (Design Automation Conference) on July 12-23, 2020 in San Francisco. Also, a customer success story using STAR 8.0 for SoC Integration will be presented at DATE at the Exhibition Theater on March 10 at 5:30 PM.