Addressing the challenges of SoC integration

Ever-growing transistor count and higher complexity make System-on-Chip integration an increasingly challenging problem, still waiting for a fully satisfactory EDA solution. Connecting IP blocks – sourced either from IP vendors or from design reuse – is just the beginning of the integration process; the difficult part is reaching the best possible PPA combination within tight deadlines, while keeping engineering costs under control. One of the EDA vendors that are specifically addressing the SoC integration challenges is Defacto Technologies, a small, fast growing company based in Grenoble, France and in San Jose, California. Defacto has recently introduced a new release of its Star platform and is working on more new features to be announced at the upcoming virtual DAC. Complementing the recent EDACafe video interview, we have asked some additional questions to Chouki Aktouf, Defacto’s CEO.


The causes of iterations

Lengthy SoC integration time is mainly due to iterations. According to Aktouf, the traditional SoC integration flow inevitably generates many iterations because the RTL code is pushed to synthesis “as is”, without enough analysis and physically aware integration. This means that many integration issues can only be discovered after synthesis.

“For example – Aktouf says – if an RTL designer doesn’t use the right technology to signoff his RTL code from the DFT point of view, after synthesis he may get a feedback from the DFT experts informing him that something is wrong when running the ATPG.” Fixing the problem clearly requires getting back to the original RTL code, modifying it, and running a new synthesis step.

With the traditional SoC integration flow, reaching compliance to many key design constraints – such as interconnection density, power, timing and DFT – may require dozens of iterations, raising the SoC cost and prolonging turnaround time. “Our purpose is to reduce the cost by reducing the engineering resources that will be involved, and go as fast as possible from the specs capturing to the tapeout. You have no choice: to reach both aggressive PPA requirements and reduce engineering cost you need to adopt a new SoC integration methodology,” Aktouf points out.


A “shift left” approach

To minimize iterations as much as possible, Defacto has adopted a quite radical “shift left” approach: taking all design constraints in consideration as early as possible in the SoC building flow. By capturing the specs and all the available information – including design collateral – at the beginning of the building process, potential problems can be uncovered at the RTL level, before synthesis.

“Our platform can detect at the RTL level the problems that you would otherwise uncover only after synthesis, such as loops, interconnections between blocks that will make place & route a burden, IP blocks belonging to the same power domain that need to be restructured to rationalize power distribution,” Aktouf explains. “This way you make it right for synthesis tools, for the physical level, avoiding painful iterations.”


Automated what-if analyses

Another shortcoming of the traditional SoC integration process – according to Defacto – is insufficient automation, especially when it comes to exploring the design space to discover the best possible solution in terms of PPA. Insufficient automation can actually become the limiting factor that prevents the design team from achieving an optimized solution, as the amount of engineering resources required to manually run multiple what-if analysis may prove excessive.

The Defacto platform addresses this problem by automatically running what-if analysis on either the RTL code or at the gate-level netlist, thus testing alternative design options that are then proposed to the designer. “For example,” Aktouf explains, “given a large gate-level netlist our tool can extract the interconnection density figures for the whole chip and propose optimization alternatives to make placement and routing easier. An option could be, for instance, pushing a block from one hierarchical level to another, obtaining a new netlist which is functionally the same but structurally different. Other what-if analysis – he continues – can be performed, for example, to reduce the area occupied by the interconnections between two blocks when a third block is in the middle: the tool can suggest to insert feedthrough logic to route interconnects through the third block, instead of bypassing it.”


Start building as soon as possible

Also contributing to reduce turnaround time is the capability of starting the SoC construction process even if some piece of RTL code is still missing. “Don’t wait until you have everything ready,” Aktouf recommends. “Start building your SoC even if for some IP block you don’t have the RTL code but just a view. It can be any view format – Excel, IP-XACT – our tool can read them all.”

“This will enable all design teams – verification, RTL, SoC integration – to start their analysis. For example, they can start exploring the clock tree structure, its impact on DFT etc. Later on, once all the RTL code is available, they can continue this process and refine their analyses,” Aktouf adds.


Complementing internally developed platforms

So far, many chipmakers have addressed the SoC integration challenges by developing their own internal tools and platforms. This, according to Aktouf, reveals that the EDA industry has been slow in coming up with solutions that live up to the customers’ needs.

“Chip making companies are always open to consider existing platforms from EDA vendors when they really are open enough and mature enough, and when they can really answer their customization requirements,” he observes.

According to Defacto, the solutions offered by EDA vendors can only succeed if they provide both flexibility and additional benefits compared to the internally developed platforms.

“First of all, we are not proposing our customers to remove their internal solution or to put it aside. We help them migrate their internal platform on top of Defacto. And when they migrate, they can still benefit from what they have already developed, with many more capabilities,” Aktouf points out.


Stepping up the standardization effort

Many professionals, both in the semiconductor and in the EDA industry, think that the ideal solution for SoC integration isn’t there yet. Aktouf, too, shares this opinion. “We believe that Defacto has the first solution that can solve some key problems, but there are many more problems still open,” he concedes.

“The industry is really going fast”, Aktouf continues, “there are several challenges ahead, for example in the verification space, at the system level space, even on bridging back end and front end. And Defacto solutions are not static. Every six months we push new capabilities because we are always driven by these needs.”

Standardization will play a key role in this continuous improvement process. “More than ever, there is a need of the industry to work together on standards at different levels: specification, verification, testbench generation, power intent, high level synthesis in terms of code generation, interfacing between software and hardware, even the build process itself,” Aktouf observes.

“A lot of standardization is needed to help the industry to come up with new solutions, to make the adoption much easier and less painful. For Defacto, as a small EDA vendor, it would be much easier if we had standards in place. So we are eager to see the industry move in this direction. We are part also of some effort on that, we are members of the Accellera IP-XACT working group,” Aktouf concludes.


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