Defacto will be exhibiting at ITC on November 3-5. Our experts will be present online to chat and share our latest features on the verification area.
In particular, this year we are announcing brand new DFT planning capabilities with a focus on power intent UPF checks during test modes. Typical features will be presented during the conference:
- New commands to checks UPF vs DFT
- Autofix available also for power structure
- Possibility to generate a new UPF with fixes
- New commands to analyze the power domains crossed by the scan chains
- New command to generate “power friendly” scan chains
As you probably know Defacto DFT solution helps DFT engineers and RTL designers in the IP DFT Signoff process by making sure their RTL designs are DFT friendly. Our DFT solution at RTL enables to check the DFT quality of a design at block, IP and chip levels before releasing the RTL to synthesis.
With this EDA tool, the ATPG process starts earlier and delivers accurate test coverage results sooner. Beyond running both the DRC and the ATPG processes at RTL, this tool is also used for testability enhancement and DFT planning in compliance with mainstream DFT methodologies.
Typical DFT features at RTL are:
- Comprehensive Design rule checks and customizable DFT DRCs
- Enabling mainstream ATPGs to be used ahead of time, without the need of synthesis
- Pinpointing the root cause of testability weaknesses graphically
- GUI-based DFT debug and extraction of cartography with testable and untestable IP/blocks
Meet us at virtual ITC for more information and demo !