Need to build a full SoC (System on Chip) with the Best trade-off ? Including: Time to Market, Power, Performance, Area, Engineering cost and IP Reuse ?


And solve key design problems before and after synthesis ? Defacto STAR makes it possible by considering much earlier SoC Design requirements: Timing, Performance, Power, Area and Security, and reducing the number of design iterations to help fitting into aggressive delivery schedules




  • SoC Integration handling a multitude of design formats
    • IP wrapping and insertion
    • IP-XACT, UPF, SDC handling
    • Connectivity insertion & checking
    • DFT Planning
  • Design optimization at Gate-level in minutes
    • Layout density improvement
    • Gate level design restructuring
    • Automatic update of design collaterals (IP-XACT, UPF, SDC)
    • ECO
  • Design Data Consistency checks and view Generation (RTL, IP-XACT, UPF, SDC, etc.)


STAR enables to design highly complex SoC to meet new market opportunities such as:

  • Turn around time
  • Cost: Engineering, Power, Area
  • Performance
  • DFT
  • Security


That's why STAR is the De Facto way to build and signoff System on Chips since 20 years !


For More Information :

Contact us 


or check our product pages