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Grenoble, France, November 17, 2022. Defacto Technologies announces that independent compliance firm SGS-TÜV has certified the compliance of Defacto’s SoC Compiler 9.0. tool and documentation and deemed to be fit for use up to ASIL D automotive design projects. Defacto’s SoC Compiler is delivered with comprehensive enablement documentation providing descriptions and best practices information.

Defacto's SoC Compiler Certified ISO26262

Defacto’s SoC Compiler is a complete SoC integration platform multidimensional and pre-synthesis with a high level of automation taking into consideration all design information, including RTL, IP-XACT, timing constraints, power, physical, and test.

Before logic synthesis, SoC Compiler enables full implementation capabilities towards IP and connectivity insertion, design editing, and views generation with real-time monitoring of the integration progress.

Silicon-proven for almost two decades, Defacto’s SoC Compiler is daily used by major semiconductor companies for large kinds of applications such as HPC, mobile, VR, AI, and more.

“Be able to provide our customers an IP & SoC design solution for automotive applications was a must. We are happy and glad today to give the possibility to our customers to use Defacto’s SoC Compiler with confidence for functional safety flows” Said Chouki Aktouf, CEO and Founder of Defacto.

 

 

 

For more information about our solution Defacto’s SoC Compiler, feel free to contact us directly at Email Contact . We will be more than happy to answer your questions and help serve your needs the best.

We look forward to working with you on automotive and functional safety applications!


 

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About Defacto’s SoC Compiler

Through a unified database with different APIs, Defacto’s SoC Compiler enables a cost-effective SoC Build & Signoff design process which opens new SoC integration and design optimization capabilities before and after logic synthesis

SoC Compiler helps to face challenges of managing jointly RTL and design collaterals during the SoC Design Assembly before logic synthesis including:

  • Power intent such as UPF
  • Timing constraints such as SDC
  • Physical design information such as LEF/DEF
  • Architectural design formats such as IPXACT
  • Design Libraries such as Liberty
  •  

Also, SoC Compiler provides a full automation to generate ready for RTL to GDS flow: RTL, UPF and SDC files by considering physical, power, timing & DFT constraints.

 

About Defacto Technologies

Defacto Technologies is a chip design software company providing breakthrough System on Chip design solutions to enhance design integration, design verification, and also the Signoff of IP cores, subsystems, and large SoCs.

By adopting Defacto’s SoC Compiler design solutions, major semiconductor companies are continuously moving from traditional and painful SoC design tasks to Defacto’s joint “Build & Signoff” design methodology. The related ROI has been proven for hundreds of projects.

Headquartered in the French Alps with a US branch in California, Defacto has today a worldwide presence with 24/7 support all over the world.

Defacto’s EDA tools previously named STAR have gained maturity for two decades not as standalone tools but as a joint solution in the process of building large SoCs.

In 2021, Defacto’s major Release 9.0 completes the process of building in front-end an SoC from either scratch and/or starting from existing projects

Consequently, it becomes a mature SoC design solution that takes user specification along with building blocks and automatically generates SoC RTL & collaterals, ready for logic synthesis.