Starting an SoC design project has always been painful given the number of design tasks from the architecture to first implementation decisions.  A successful start has a significant impact on the next design tasks and TAT, up to the tape out. If we look at today’s SoCs, the number and variety of IPs keep increasing and same for the complexity of architectures which leads to very complex clock trees, power architecture, etc., the verification process is also a real burden which needs a lot of attention. In summary, there is a requirement to put in place cutting edge design methodologies at the front-end to make the SoC build faster, and to generate the first packages and data for synthesis and simulation design steps.


This March 2023, Defacto is announcing the new Major Release of its solution: SoC Compiler 10.0. This is an important turning point for the company which also celebrates its 20th anniversary this July right during DAC. For 20 years, Defacto provided breakthrough innovation in the EDA and built a real expertise in particular on the management of the RTL. They are now recognized and used by most of the major semiconductor companies.


This SoC Compiler 10.0 Major Release will address several key challenges of Defacto’s customers. The main challenge is the fact there was no solution in the market to make the SoC integration considering jointly RTL and IP-XACT. More technically, there is a real need to support various formats for IPs and connectivity, and both need to be considered since: IP-XACT is not able to fully describe the complexity of designs for integration and RTL alone requires an additional effort to make connections between groups of ports belongs to same architecture protocol. Worth mentioning that this requires supporting the complete RTL and IP-XACT versions (Verilog, System Verilog, VHDL, IP-XACT 2009, IP-XACT 2014).



Today’s workaround is to redesign IPs dropped in advance System Verilog construct to align with what IP-XACT 2014 can support for the connections. This workaround is tedious, with a high risk of breaking existing design, time consuming and hard to maintain. Defacto’s SoC Compiler V10.0 is the first design solution to consider at the same level both IP-XACT and RTL to face SoC design integration challenges containing the increasing design complexity with reasonable performances.


Along with that, Defacto’s SoC Compiler 10.0 comes with brand new IP-XACT features which enable a complete support of the Accellera standard for both 2009 and 2014; for the integration but also for the management of registers and system memory map.


In parallel, we observed a real shift in the EDA tool usage, and it seems more than ever a requirement for the users to have an interface, not only using Tcl but also in Python. Defacto is providing since more than 10 years Python, Perl and C++ interfaces for his tool, but in SoC Compiler 10.0, Defacto is taking Python support to the next level, with 100% object-oriented APIs.


Defacto’s SoC design solution key differentiator is the unified management of design data including RTL/IP-XACT, UPF, SDC, etc. along with the link with physical design information which enables power aware, physical aware, clock aware, DFT aware, etc. assembly.

No doubt this unified methodology goes at the right direction to cost-effectively build complex and large SoCs.