In preparation for DAC Daniel Nenni from Semiwiki had a conversation with Defacto CEO: Dr. Chouki Aktouf.
I noticed this year at DAC is the 20th anniversary of the company, congratulations on your success!
It is a really important year for Defacto and July is an important month. The company was founded in July 2003.
During these 20 years we proved our added value in the SoC building process pre-synthesis. In particular in the reduction of the design cycles and the PPA optimization. Today, we are proud to count most of the top 20 semiconductors companies as regular users of Defacto’s SoC Compiler.
So, definitely, after 20 years, we are confident to say that for many front-end SoC designers our EDA tools become the “de facto” and their “SoC Compiler” in the early SoC design building process managing RTL, IPXACT and design collaterals!
We will celebrate the 20th year anniversary at DAC, where we will be having several announcements in terms of success stories and tool major capabilities. Several customers will be coming to our booth (#1541) to share their experience using our solutions and how they are benefiting from them. Many events and surprises are also planned to celebrate properly this 20th anniversary!
In parallel Defacto announced a new Major Release of its SoC Design solution. Could you please elaborate?
Exactly, this is the 10.0 Major Release of Defacto’s SoC Compiler. This release will bring a lot of announcements in terms of features, capabilities, and better performance along with first customers statements and testimonies when using this Release for large SoCs. In summary, the main announcements we will be showing at DAC about this major release, beyond the maturity of the Defacto design solution, is how much it becomes easy to use by RTL designers and SoC design architects. We are simplifying the SoC building process pre-synthesis from user SoC design specifications to the generation of the whole package, RTL and design collaterals, ready for synthesis and for design verification. This will be the main addressed topic by the Defacto team at DAC.
As I remember, SoC Compiler is an integration tool at the front-end. What about help for back-end designers?
Absolutely! our EDA market positioning for decades is clear. Our design solutions help at the front-end when starting the SoC building process but the way we manage the RTL and design collaterals is not independent or uncorrelated from the back-end. Actually, back-end designers can provide the tool with physical design information. And then the tool will generate, for example, the top level of the RTL which is physically aware. Which means that this physically aware RTL and the related design collaterals can be directly synthesized which usually leads to better PPA results. In summary, this connection between the front-end and the back-end is where back-end designers, and also SoC design architects find a unique value compared to other EDA tools.
Are the benefits mainly speeding up the design process? PPA? Or both?
Good question. Definitely, speeding-up, shortening the design cycles/process is key since we are providing high level of automation. But getting a better PPA is also an important expectation when using Defacto. What I just mentioned earlier for the physically aware SoC integration definitely impact the PPA. Synthesis and P&R EDA tools will definitely do a better job.
In addition, our solution also helps directly optimize PPA by managing RTL connectivity with feedthroughs. for. Also, during DFT coverage enhancement and test point insertion, our design solutions automates the process of exploring and inserting test points at RTL to ensure high coverage with the lower area overhead. So, in summary both PPA and design cycles are addressed when using our design solution.
Do you manage design collaterals like UPF and SDC compared to RTL?
This is a major difference between Defacto’s solution and competition. In summary, we don’t manage only the RTL when building the SoC and generating the top level. We consider at the same time RTL and the design collaterals. At the same time, we mean managing incoherency problems between the RTL database, the SDC database, the UPF database, the IP-XACT database, etc. Also generating missing views to speed up the SoC building process. In other words, the joint management of RTL and design collaterals in a unified way is what makes Defacto’s SoC Compiler unique.
I always knew the tool to integrate IPs and build the top level. Is it possible to generate the design for synthesis and simulation tool?
This is exactly what we do. Building, integrating, inserting IPs, inserting connections, these are the daily capabilities the tool provides to the user but actually, what we are also enabling is what I said at the beginning, the generation of RTL and design collaterals.
If you need to rely to the tool to translate a specification of an SoC to the Top level, this becomes possible. How? We can share with the users at DAC through demos, how the tool interoperates with IP configuration tools to shorten the path between the specification to the Top level generation. So, the generation is today key in the automation that is provided by our design solution.
We hear a lot about Python interest in EDA, do you provide a Python API?
This is quite funny because from the past years people started to come saying: “I am a designer but in my engineering school I was more familiar with Python than Tcl, can you help us?” So, the answer is YES, today we see more and more designer’s pick-up with Python, expecting the tool to be used in Python. Why? Because for them it is easier to script in Python.
We fully support Python and the way we handle Python is 100% object-oriented. For people who have a Python culture, they should visit our booth, they will like the examples that our team will share with them!
Do you provide any checking capabilities like linting?
Checking engines are underlying in our design solution. When you start building the chip, it’s not only about editing or integrating features. The tool must provide checks to make sure the building process is reliable and correct by construction. So, we have many checking capabilities basic linting for the RTL, and each of the design collaterals along with the coherency between them. Static signoff is also provided for DFT, clocking, …. And more importantly, all these checking capabilities can be customized and extended by the user.
After 20 years and the focus on SoC Integration are you still providing DFT within SoC Compiler?
You know, we started with DFT solution a long time ago but still DFT is part of the offer. Our DFT solution is among the most mature ones in the market. We don’t really overlap with DFT implementation tools. We provide an added value at RTL in terms of DFT signoff, planning, exploration. So, yes in summary we are still a key provider of DFT solutions, for both RTL designers and DFT experts.