STAR RTL Design Checker helps RTL Designers and Design Managers to better contain the increasing complexity of the RTL code (Verilog, VHDL, System Verilog).

Code Complexity Metrics (CCM) measure the level of complexity of an RTL code and help preventing synthesis and post-synthesis problems by pinpointing on critical areas of the code through the design hierarchy. For an RTL designer, Defacto CCM measures help flagging poorly written RTL code. For a Design Manager, such measures help estimating design effort given a new written RTL code.




Key Features

  • Data structure extraction (Component, ports, instances, nets, connections)
  • Cyclomatic Code Complexity extraction
  • Multi HDL language support (Verilog, VHDL, System Verilog)


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