The complexity of system on chips keeps increasing and SoC designers keep having lot of pressure to deliver and keeping the cost as low as possible. To stay within a PPA budget (power performance area), it's challenging daily for designers. Defacto’s SoC Compiler keep providing innovative solutions to increase the productivity of designers.
During this webinar, we’ll talk about power. Beyond an automated generation of the power intent files before synthesis, recently Defacto has released key capabilities at the front-end to better manage the power intent.
- First capability is the promotion of the UPF; Given power intent files for different IPs, designers have today the ability to assemble UPF files and promote the power intent automatically to the top.
- The second feature is the other way around called UPF demotion; Given an existing SoC or subsystem, a designer can extract the power intent file.
More precisely, during this webinar our experts will cover a complete power intent management methodology with a particular focus on integration needs pre-synthesis: how to generate UPF from scratch, update the UPF after design changes, demote UPF for reuse purpose and promote the UPF based on the integration.
AUDIENCE: CAD Manager, Architects, CAD Engineer, Designers, Integration teams, Verification teams and UPF experts!
- Chouki Aktouf: CTO at Defacto
- Arthur Kalsing: Senior R&D engineer at Defacto & UPF Expert
WEBINAR RECORD AVAILABLE HERE