[Please note that this page is presenting an old version of our solutions. For an up to date version of our SoC Compiler please go to Front-end SoC Integration]
RTL Design Builder covers editing and code generation needs at RTL. It replaces complex and hard to maintain in-house scripts and tools. Through basic and advanced editing capabilities, this tool shortens the path to synthesis-ready RTL code for complex IPs and SoCs.
Typical RTL Design Builder features are :
- Basic and advanced commands with generation of ready for synthesis RTL code
- Easy development of Tcl applications for any specific editing need at RTL
- Debug environment with cross-probing between RTL and schematic
- Seamlessly integrated with the other STAR EDA tools
Additional STAR EDA Tools :
- RTL Design Checker
- RTL Design For Test
- RTL low Power
- Padring
- RTL IP Integration
- RTL Code Complexity Metrics
Build custom and Language Independant Design Application at RTL with :
