[Please note that this page is presenting an old version of our solutions. For an up to date version of our SoC Compiler please go to Checks and Verifications]
RTL Design Checker enables complete access to the design database through queries that allow in-depth design exploration and GUI debugging tasks. The tool automatically and cost-effectively performs general purpose connectivity checks for a large number of pins simulation-free. Through the design hierarchy, this tool helps verify and debug multiple connections under different modes of operation within the same run.
Typical RTL Checker features are :
- In-depth design exploration through Tcl interface
- Simulation-free Pin-to-Pin tracing
- Easy creation of Tcl custom checks
- GUI exploration
- Cyclomatic Code Complexity extraction
- Seamlessly integrated with the other STAR EDA tools
Additional STAR EDA Tools :
- RTL Design Builder
- RTL Design For Test
- RTL low Power
- Padring
- RTL IP Integration
- RTL Code Complexity Metrics
Build custom and Language Independant Design Application at RTL with :
