After logic synthesis, STAR helps reaching power, performance and area (PPA) requirements for complex SoCs is becoming a real challenge. Large design netlists are restructured and optimized to reach aggressive PPA requirements, cost-effectively.
Benefits
- Save Area – Between 5 to 10%
- Reduce design optimization runtime from days to hours
- Lower the burden on physical designers to reduce TAT (Turn Around Time)
- Eliminate error-prone manual netlist editing, generate “correct-by-construction” netlists
- Reduce project development schedule by several men-months
Features
- Density improvement & Hierarchical manipulation
- Power and Physically Aware Design Restructuring
- Multi-view update including UPF & SDC
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