[Please note that this page is presenting an old version of our solutions. For an up to date version of our SoC Compiler please go to Products and Solutions]
RTL DFT enables DFT engineers and designers to check the DFT quality of a design at block, IP and chip levels before releasing the RTL to synthesis. With this EDA tool, the ATPG process starts earlier and delivers accurate test coverage results sooner. Beyond running both the DRC and the ATPG processes at RTL, this tool is also used for testability enhancement and DFT planning in compliance with mainstream DFT methodologies.
Typical RTL DFT features are :
- Comprehensive Design rule checks and customizable DFT DRCs
- Enabling mainstream ATPGs to be used ahead of time, without the need of synthesis
- Pinpointing the root cause of testability weaknesses
- GUI-based DFT debug and extraction of cartography with testable and untestable IP/blocks
- Seamlessly integrated with the other STAR EDA tools
Additional STAR EDA Tools :
Build custom and Language Independant Design Application at RTL with :
